1. Field of the Invention
The present invention relates to a semiconductor packaging technique, and more particularly, to a structure and method to join a semiconductor package and a substrate.
2. Description of the Related Art
As integrated circuit chips become more integrated, the chips tend to receive and transmit more input and output signals. Accordingly, semiconductor packages need to accommodate more, e.g., denser, external connection terminals in smaller or more limited areas. Ball grid array (BGA) packages, for example, have addressed such needs.
A lead frame package may use leads as external connection terminals, while a BGA package may use solder bumps as external connection terminals. The leads in a lead frame package may be provided along a semiconductor chip in a one-dimensional arrangement. The solder bumps in a BGA package may be provided on one surface of a semiconductor chip in a two-dimensional arrangement. As shown in FIG. 1, a leadframe package 10 may include a semiconductor chip 12 and leads 11 arranged along the semiconductor chip 12. As shown in FIG. 2A, a BGA package 20 may include a semiconductor chip 22 and solder bumps 21 arranged on one surface of the semiconductor chip 22.
FIG. 2B is an enlarged cross-sectional view of area A in FIG. 2A. Referring to FIGS. 2A and 2B, the BGA package 20 may include a printed circuit board 24 having an upper surface 24a and a lower surface 24b. An integrated chip 22 may be mounted on the upper surface 24a of the printed circuit board 24. An encapsulant 23 may seal a raised portion formed on the upper surface 24a of the printed circuit board 24. Solder bumps 21 may be provided on the lower surface 24b of the printed circuit board 24. A copper wiring layer 25 may be formed on the lower surface 24b of the printed circuit board 24. An insulating protective layer 26 may be provided on the copper wiring layer 25 and provide openings therethrough to expose a portion of the copper wiring layer 25. The solder bumps 21 may be attached to the exposed copper wiring layer 25.
FIG. 3 is a cross-sectional view of a structure for joining a semiconductor package 20 to a package mounting substrate 30. Referring to FIG. 3, the semiconductor package 20 may be mechanically and electrically connected to the package mounting substrate 30 using a solder bump 21. The package mounting substrate 30 may have a copper wiring layer 31 and an insulating protective layer 32.
The conventional structure may have several drawbacks. For example, the coefficient of thermal expansion of the semiconductor package 20 may be different relative to that of the package mounting substrate 30. A difference in the coefficient of thermal expansion may cause stresses concentrated on the solder bump 21. Various faults, therefore, may be generated at a solder bump joint. Thus, after an assembly process, for example, the semiconductor package 20 may go through a test process. The test process may involve a temperature cycle. Since the semiconductor package 20 and the package mounting substrate 30 may expand and/or contract differently, e.g., as shown in FIG. 4A, stresses in opposite directions may apply to the semiconductor package 20 and to the package mounting substrate 30. As a result, cracks such as shown in FIG. 4B may occur at the interferences between the solder bump 21 and the copper wiring layers 25 and 31. Such cracks may cause faults in the connection and thereby cause test failure. Furthermore, such cracks may cause undetected weakness in the connection and subsequent external shocks, e.g., during further assembly or later use, may result in connection failure.